Title: SpaceCubeX: Initial Simulation-level Results of Hybrid On-board Processing Architectures
Presenting Author: Matthew French
Organization: USC / ISI
Co-Author(s): Andrew Schmidt, Gabe Weisz, Tom Flatley, Gary Crum, Jonathan Bobblit, Carlos Villalpando, Robert Bocchino

Abstract:
The SpaceCubeX project addresses NASA Earth Science missions and climate architecture plan and its underlying needs for high performance, modular, and scalable on-board processing. Missions such as (P)ACE, HyspIRI, GEO-CAPE, ICESat-2, and ASCENDS are specifying instruments with significantly increased temporal, spatial, and frequency resolutions and moving to global, continuous observations. These goals translate into on-board processing throughput requirements that are on the order of 100-1,000x more than previous Earth Science missions for standard processing, compression, storage, and downlink operations. SpaceCubeX addresses these needs, by researching and developing a Hybrid Multi-core CPU/FPGA/DSP Flight Architecture. Recent studies have shown that in order to realize mission size, weight, area, and power (SWAP) constraints while meeting inter-mission reusability goals, compact heterogeneous processing architectures are needed. In a heterogeneous architecture, general OS support, high level functions, and coarse grained application parallelism are efficiently implemented on multi-core processors, while a co-processor provides mass acceleration of high throughput, fine-grained data parallelism operations, to achieve high performance robustly across many application types. Hybrid architectures represent a significant departure from traditional homogeneous avionics. SpaceCubeX provides a structured approach to assess and develop hybrid architectures, fundamentally changing the avionics processing architecture development process. This presentation provides an overview of the results of the first year's efforts, in which the first spiral of our heterogeneous evolvable testbed has been completed, 5 different heterogeneous board architectures have been represented in our framework, and initial results of over 200 benchmark applications have been collected.