Title of Presentation: Smart Payload Development for High Data Rate Instrument Systems

Primary (Corresponding) Author: Charles D. Norton

Organization of Primary Author: Jet Propulsion Laboratory, California Institute of Technology

Co-Authors: Paula J. Pingree, Jean-Francois Blavier, Dmitry Bekker , and Lucas Scharenbroich

Abstract: Instruments proposed to satisfy measurement objectives of future NASA AOs, and the NRC Decadal Survey missions, will need on-board processing technologies to support autonomy, operations, and science data processing. Traditionally, payload design flows down from measurement objectives, to algorithm design, to realization on a computational platform with limited capabilities. We will describe a more integrated payload systems design approach applicable to the next generation of high data rate instruments for Earth and planetary systems, as well as the current challenges in implementing state-of-the-art on-board algorithms on the latest FPGA hardware.

Two example systems will be discussed; the MATMOS FTIR spectrometer design and a hyperspectral Sea, Water, Ice and Land (SWIL) classification algorithm. We will show, via demonstration of a sample FFT algorithm implementation that is part of our conceptual FPGA-based computational architecture, how smart payload development techniques for the MATMOS FTIR spectrometer, proposed to Mars Scout, can reduce on-board instrument data volume by a factor of 80. The originally proposed MATMOS design used 2 RAD 750 processors requiring more power, mass and volume than the FPGA solution. We also discuss optimization challenges in synthesizing to FPGA fabric a legacy C-code SWIL algorithm (for the Hyperion instrument deployed on EO-1). Our initial results show that a non-optimized algorithm uses 34% of the fabric’s DSPs for floating point computation, but the more desirable optimized approach uses 170%, inhibiting synthesis for the selected single FPGA.

Such technology challenges associated with designing on-board data processing payload systems for advanced instruments will be described. We assert that designing an FPGA-based computational instrument platform would serve as a sharable component to meet the on-board processing requirements of such instruments.