Title of Paper: Overview of the MATCH Compiler for Compiling
MATLAB Programs into Hardware
Principal Author: Dr. Prith Banerjee
Abstract: Efficient high-level design tools that can map
behavioral descriptions of signal and image processing applications to FPGA
architectures are one of the key requirements to fully leverage FPGAs for high-throughput
computations and meet time to market pressures. Currently, most FPGA designs
are entered at the level of Register Transfer Level (RTL) VHDL or Verilog. It
is widely recognized that there is a need for design tools at the high level
using languages such as C/C++ or MATLAB. MATLAB is an extremely popular
language in the signal and image processing community with over 500,000 users.
A direct synthesis path from MATLAB into hardware would be very useful.
The MATCH compiler at Northwestern Universisty takes as input algorithms
described in MATLAB, and generates Register Transfer Level (RTL) VHDL. The RTL
VHDL then can be mapped to FPGAs using commercial tools. The input application
is mapped to multiple FPGAs by parallelizing the application and embedding
computation
and synchronization primitives automatically. Our compiler infers the minimum
number of bits required to represent the variables through a precision
inferencing analysis framework. The compiler can leverage optimized
Intellectual Property (IP) cores to enhance the hardware generated. The
compiler also exploits parallelism in the input algorithm by pipelining in the
presence of resource constraints. We demonstrate the utility of the compiler by
synthesizing hardware for a couple of signal/image processing algorithms and
compariing them to manually designed hardware.